Duobinary signaling and decoding vin
An embodiment of the invention is related to optoelectronic circuits and, in particular, an optical receiver designed to receive a binary coded duobinary signaling and decoding vin signal as input. Other embodiments are also described and claimed. Optical receivers are used in optical transponders or transceivers, to enable communications equipment to operate over fiber optic lines. High data rate in this case refers to 5 gigabits per second Gpbs and higher. NRZ OOK coding is an example duobinary signaling and decoding vin the more general binary coding format, where data is translated into a stream of symbols where each symbol can have one of only two values, and accordingly the transmission line duobinary signaling and decoding vin has one of only two stable states.
Duo-binary data formats are less susceptible to single duobinary signaling and decoding vin fiber chromatic dispersion, as well as other link distortions. However, generating duo-binary signals on the transmit end of a fiber link typically requires the use of costly and relatively uncommon optical and electrical components. The embodiments of the invention are illustrated by way of example and not by way of limitation in the figures of the accompanying drawings in which like references indicate similar elements.
An embodiment of the invention is directed duobinary signaling and decoding vin a receiver that may be used to operate with longer fiber reaches, without the need for fiber dispersion compensation. An optical to electrical converter has an input to receive data that has been encoded by a transmitter not shown into a binary coded signal and transmitted over an optical transmission line e.
The duobinary signaling and decoding vin may also include an amplifier stage that amplifies the resulting electrical signal from the detector. Next in the chain is a duo-binary encoder whose input is coupled to an output of the converter.
The encoder applies duo-binary encoding to the signal from the converter, to create a duo-binary, three level signal, e. The duo-binary encoder reduces high frequency signal distortions in the electrical signal that were caused by fiber dispersion.
Next, an output of the encoder is coupled to an input of a duo-binary decoder The decoder performs a duo-binary decoding function, to recover a binary coded signal.
A decision circuit follows, whose input is coupled to an output of the decoder. The decision circuit makes binary decisions on the output of the decoder which may be a noisy signal. The resulting decision stream at the output of the decision circuit may then be fed to a re-clocking circuit not shown. That circuit re-clocks the data into the centers of their respective bit cells to provide a more accurate and more easily usable representation of the data stream that was transmitted at the other end of duobinary signaling and decoding vin optical link not shown.
A receiver that uses the optoelectronic circuit of FIG. In other words, the optical signal input to the converter may be in a commonly transmitted binary format.
In addition, the receiver obtains most of the dispersion tolerance of duo-binary transmissions, by using the combination of the duo-binary encoder and duo-binary decoder at the receiving end, to help reduce high frequency signal distortions that were caused by fiber dispersion in the fiber optical fiber transmission line. The data input to the optoelectronic circuit of FIG.
In addition, the data to be transmitted should be differentially encoded pre-coded duobinary signaling and decoding vin to transmission, such as described by the following equation: This type of differential coding may be implemented using an duobinary signaling and decoding vin gate that is operating on two inputs, the input data stream and the exclusive-OR output delayed by one bit.
This pre-coding operation duobinary signaling and decoding vin reduce the chances of error propagation in duo-binary data. Note that in this case, the duo-binary data is generated at the receiver, rather than at the transmitter. Other ways of differentially encoding the transmitter data are possible.
Turning now to FIG. The receiver described here obtains most of the dispersion tolerance of duo-binary transmission, while using a standard low cost NRZ OOK transmitter to generate the example binary coded optical signal that is input to the receiver. As suggested above, the data to be transmitted may be differentially encoded pre-coded prior to transmission. In the receiver depicted in FIG. The signal, in this case, a binary coded current signal, is input to a transimpedance amplifier TIA whose output is coupled to a variable gain amplifier VGA This helps reduce common mode noise in the rest of the receiver circuitry and provides the complementary inputs to the full wave rectifier circuit described below.
Other configurations of an optical to electrical converter are possible. Next in the chain are a pair of duo-binary filters DBFthat perform an analog duo-binary encoding function on the binary data at the respective complementary outputs of the VGA The DBF is an analog, low-pass filter having a defined response and bandwidth e. The DBF operates by introducing controlled, inter-symbol interference, to generate the three level signal. In some cases, the DBF reduces the signal to random noise power ratio by about 3 dB.
However, high frequency signal distortion caused by fiber transmission line dispersion is also reduced by these DBFs That alternative may yield equivalent performance and will eliminate one of the DBFs Another implementation could use an electronically tunable DBF, to allow duo-binary encoding for different data rates or to duobinary signaling and decoding vin to binary decoding assuming in this example that the optical data input is binary NRZ coded.
Yet another implementation could use a single, differential DBF, instead of the two, matched single ended DBFsshown. Other implementations for a duo-binary encoder are possible. This bipolar, three level signal drives the complementary inputs of a broadband, full wave rectifier FWR circuitwhich performs an analog, duo-binary decoding function.
A forward bias current I 1 is applied to the FWR circuit, for duobinary signaling and decoding vin rectifier performance. Resistors R 1 and R 2 are duobinary signaling and decoding vin to tap into the signal path to provide bias current to the diodes, as well as provide impedance matching.
Duobinary signaling and decoding vin full wave rectifier circuit designs duobinary signaling and decoding vin possible. Besides decoding the duo-binary signal from the DBFs, the FWR circuit is also used to detect an average signal amplitude, which is the parameter that is driving a gain control feedback loop that is used in this embodiment, to stabilize duobinary signaling and decoding vin encoded signal at the input of the FWR into a proper range.
This detected DC voltage serves here as feedback for the gain control loop, which servos the gain of the VGAto provide a relatively high signal level into the FWR This helps reduce losses that are due to the FWR's non-ideal rectifier characteristics, therefore improving receiver performance. The signal detection output taken from resistor R 1 in this case is temperature compensated using operational amplifier or instrumentation amplifier and schottky diodes D 5 and D 6 that are matched to the FWR diodes D 1 -D 4.
Note the following example relative resistor values: The temperature compensation is achieved by comparing the sensed power to a reference voltage V R at the inputs of an operational amplifier that is configured as an integrator The integrator filters the feedback signal, and drives the gain control input of the VGA as shown.
Other compensation circuits are possible. Given that the output of the FWR is binary, and in this case differential, the circuitry following the FWR should be capable of supporting the full bandwidth of the binary coded, Data In signal. Other types of decision circuits may alternatively be used here.
Next, the decision stream is fed to a clock and data recovery circuit CDRwhich recovers a clock from its input, and re-clocks the data from the limiter amplifier into the center of the duobinary signaling and decoding vin bit or cell. This provides an accurate representation of the received data stream, for use by subsequent higher layer logic not shown.
Note that the limiter amplifier and CDR may be conventional circuits such as those particularly designed for NRZ binary coded data inputs, and are often integrated into a single chip.
It should be noted that the input signal to the limiter amplifier may be offset with an adjustable threshold voltage, to reduce bit error rate or improve receiver sensitivity by compensating for signal or noise asymmetries.
This threshold voltage can be set once, or can be actively controlled in a servo loop, to reduce bit error rate in a link using forward error correction. The threshold voltage is converted to a differential signal in this case using a differential output amplifier DA and is driven into the signal path by way of resistors tapping into the data path as shown.
A variation here could be to use a single ended, instead of differential, threshold voltage tapping into one side of the limiter amplifier's differential input. In another alternative, a microcontroller may be added along with digital to analog D to A converters, to provide digital control of the threshold voltage V Tthe current source bias I 1I 2and the reference V R duobinary signaling and decoding vin the gain control loop.
A combination of analog to digital converters, D to A converters, and a microcontroller, could also be substituted for the gain control feedback path, taking the place of differential output amplifier and integrator In operationa binary optical signal containing data is received.
As duobinary signaling and decoding vin above, this may be an NRZ OOK transmitted signal that does not duobinary signaling and decoding vin special transmit side components, but rather may be generated using a relatively low cost, standard OOK transmitter such as an externally modulated laser.
The received signal is then converted into a binary electrical signal operation This may be done using a conventional, photo diode detector. Next, the binary electrical signal is duo-binary encoded operation followed by being full wave rectified operation In most cases, the encoded signal will be relatively noisy, such duobinary signaling and decoding vin binary decisions will need to be made on the full wave rectified signal operation The above-described approach in FIG.
If the CDR circuit is not included, then an optical duobinary signaling and decoding vin can be implemented in a relatively small form factor optical transceiver. An example of such an optical transceiver is shown in Duobinary signaling and decoding vin. The small form factor transceiver has a pair of sockets formed in a housing, to receive a pair of optical fiber plugs, and has an electrical output that provides a differential, binary electrical signal containing the received data stream.
The receiver circuitry is integrated entirely within the housing. The example circuit schematic of FIG. This may also help reduce cost and power dissipation within a small and low cost product such as XFP or X2 form factor optical communications elements.
The invention is not limited to the specific embodiments described above. For example, the entire functionality of FIG. As an alternative, the optoelectronic circuit may be integrated within a receive optical subassembly as mentioned above.
Accordingly, other embodiments are within the scope of the claims. Year of fee payment: An optoelectronic circuit has an optical to electrical converter, a duo-binary encoder with an input coupled to an output of the converter, and a duo-binary decoder having an input coupled to the output of the encoder. A decision circuit duobinary signaling and decoding vin an input coupled to an output of the decoder is also provided.
An optoelectronic circuit comprising: The circuit of claim 1 further comprising: The circuit of claim 1 wherein the decision circuit comprises a limiter amplifier having a differential input coupled to a dual output of the full wave rectifier.
The optoelectronic circuit of claim 5 wherein the duo-binary filter and full wave rectifier circuit are analog circuits. The optoelectronic circuit of claim 5 further comprising a small form factor housing in which the converter, filter, full wave rectifier circuit, decision circuit, and feedback control loop are integrated.
The optoelectronic circuit of claim 5 wherein the full wave rectifier circuit comprises a plurality of resistors coupled to a plurality of diodes arranged as a bridge rectifier, to provide a diode bias input and return and b impedance matching to the full wave rectifier circuit.
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